Continuing advances in miniaturization and densification of integrated circuits have led to smaller areas available for devices such as transistors and capacitors. With shrinkage of the cell size, maintaining a sufficient amount of cell charge storage capacitance is a challenge in a dynamic random access memory (DRAM).
Several techniques have been developed to increase the storage capacity of a capacitor in a limited space. One such technique is to fabricate a cup-shaped bottom electrode defining an interior surface and an exterior surface within a container formed in an insulative layer. A recess between adjacent bottom electrodes is formed in the insulating layer to expose a portion of the electrodes' exterior surfaces. A capacitor dielectric and then a top electrode are deposited over the interior of the cup-shaped bottom electrode and the interior of the recess. The structure provides additional capacitance.
Conventionally, the bottom electrode is formed of N-type hemispherical grain silicon (HSG). Using a double-sided HSG bottom electrode provides a higher surface area for increased capacitance. However, the growth of HSG on the exterior container surface can cause cell to cell shorts, requiring the space between containers to be enlarged.
Thus, a need exists for a structure and process therefor that overcomes such problems.